1. Field of the Invention
The present invention relates to the estimation of Elmore delays within circuit designs. More particularly, it relates determination of Elmore delays and a 50% point delay in a timing verifier using information relating to charges of MOS devices.
2. Discussion of the Related Art
The Elmore delay, first presented in W. C. Elmore, xe2x80x9cThe Transient Response of Damped Linear Networks with Particular Regard to Wide Band Amplifierxe2x80x9d, Journal of Applied Physics, Volume 19, 55-63 (January 1948), has been used extensively as a measure of delay for RC interconnect and for MOS circuits. Given an RC tree, the Elmore delay is computed using an equation based upon the resistance and capacitance of different paths to a defined output.
Elmore delay calculations are used in timing verification of circuits. In designing circuits, it is important to rapidly identify circuit paths of concern. One method for identifying potential problems with a circuit design is by reviewing the timing of Elmore delays within the circuit. If certain circuit paths appear to have difficulties, then a circuit simulator can be used to check these paths for potentially necessary modifications. For effective verification, a timing verifier needs to identify critical circuit paths quickly. In order to do this, various models for determining Elmore delays have been created. In particular, a resistance and capacitance are used to approximate each MOS device within the circuit by a corresponding RC structure for the calculation of the Elmore delay. Algorithms have also been developed to compute an Elmore delay for a MOS circuit. T. M. Lynn and C. A. Mead, xe2x80x9cSignal Delay and General RC Networksxe2x80x9d, IEEE Transaction on Computer Aided Design, Vol. CAD-3,4, 331-349 (October 1984), and D. Martin and R. C. Rumin, xe2x80x9cDelay Prediction from Resistance-Capacitance Model of General MOS Circuitsxe2x80x9d, IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems, Vol. No. 12, 7, 997-1003 (July 1993), disclose various procedures for estimating Elmore delays for MOS devices within a circuit. In such algorithms, the resistance and capacitance models used to approximate the MOS circuit are a great source of error in computing the Elmore delay. Part of the difficulty in determining such values is that the resistance and capacitance depends upon the structure of the circuit, not solely each device itself.
In determining Elmore delays for timing verification, it is important not to miss any critical paths. Therefore, timing verifiers typically have ignored the effect of the circuit itself on the determination of the resistance and capacitance used to represent each device. Rather, timing verifiers have relied upon determinations of maximum and minimum capacitance and resistance models so that no critical paths are missed. This, however, results in highly inaccurate models and the identification of many false positives for critical paths. Each critical path identified must be further analyzed and verified using more accurate methods of circuit simulation. Therefore, the identification of many false positives results in significant time delays and additional work. Therefore, a need exists for more accurate determinations of Elmore delays within timing verifiers.
The present invention overcomes many of the deficiencies of the prior art by providing a method and apparatus for generating accurate models for Elmore delays from accurate estimates of charges. According to one aspect of the invention, performance of different circuit structures is simulated based upon characteristics of the circuit being designed to generate models for Elmore delays with different basic circuit structures. According to another aspect of the invention, models for determining Elmore delays are generated as functions of specific circuit configurations, device widths, and charges.
According to another aspect of the invention, the models for the Elmore delays are used in a timing verifier to determine critical paths within a circuit design. Specifically, the system analyzes the design of the circuit to determine a path. It then uses the appropriate model for each device to determine individual Elmore delays. Finally, the Elmore delay for each of the devices is combined to generate the Elmore delay for each path.
According to another aspect of the invention, a simulation procedure is also used for determining charges for each of the MOS devices in the circuit. As in generating Elmore delay models, simulations are run on various circuit configurations to determine charges for basic circuit structures. When the charge of the device needs to be used within the timing verifier, the appropriate model is selected.